1. Field of Invention
The present invention relates to a method for manufacturing semiconductor devices. More particularly, the present invention relates to a method for manufacturing the cylindrical lower electrode of a DRAM capacitor.
2. Description of Related Art
Dynamic random access memory (DRAM) having a storage capacity smaller than one million megabits (Mbits) generally has a two-dimensional or so-called planar type of capacitor structure. However the planar type of capacitor occupies a large surface area of the semiconductor substrate, and hence is unsuitable for forming, high-level integrated circuits. For DRAM having storage capacity greater than four Mbits, three-dimensional capacitor structures such as the stack type or the cylindrical type of capacitor are generally used.
FIGS. 1A through 1F are schematic, cross-sectional views showing the progression of manufacturing steps according to a conventional method of forming the cylindrical lower electrode of a DRAM capacitor. First, as shown in FIG. 1A, a semiconductor substrate 10 that has source/drain regions (not shown) thereon is provided. Thereafter, an insulation layer 12 for example, a silicon oxide layer is deposited over the substrate 10, and then a contact opening 14 is formed in the insulation layer 12. Next, a conductive layer 16, for example, a polysilicon layer, is formed, filling the contact opening 14 and covering the insulation layer 12. The conductive layer 16 inside the contact opening forms a contact that serves as an electrical connection between the source/drain region and the subsequently formed capacitor.
Next, as shown in FIG. 1B, photolithographic operations are carried out by first forming a photoresist layer 18 over the conductive layer 16 and then patterning the photoresist layer 18.
Next, as shown in FIG. 1C, using the photoresist layer 18 as a mask a portion of the conductive layer 19 is etched. By controlling the etching period a pre-defined layer of the conductive layer 16 is removed to form a protruding block 20. Finally, the photoresist layer 18 is removed.
Next, insulating material is deposited over the conductive layer 16 and the protruding block 20 as shown in FIG. 1D. Thereafter, the insulation layer is etched back in an anisotropic etching operation to form spacers 22 on the sidewalls of the protruding block 22.
Next, as shown in FIG. 1E, using the spacers 22 as a mask, the conductive layer 16 is again etched to form a cylindrical-shaped lower electrode structure 16a. In the process, sharp spikes 24 are also formed on the inner sidewalls of the spacers 22. The layer of conductive material to be removed from the conductive layer 16 is again controlled by the etching period.
Finally, as shown FIG. 1F, the spacers 22 are removed to form the cylindrical lower electrode 16a of a capacitor above the insulation layer 12 using a wet etching method.
In the aforementioned method or forming the cylindrical lower electrode 1 6a of the capacitor the spacers 22 that act as a mask layer must be formed by first forming an insulation layer over the substrate 10. Next, the insulation layer is etched back anisotropically to form the spacers in the sidewalls of the protruding block structure 20. The processing steps are complicated and hence often lead to various kinds of errors that may affect the product yield. Furthermore sharp spikes 24 are frequently formed on top of the cylindrical lower electrode 1 6a. These sharp spikes 24 can easily become a particle source. Hence, when a dielectric layer is subsequently formed over the electrode 16a, the step of immersing the substrate in an acid bath will lead to contamination and the production of leakage current in an operating capacitor.
In light of the foregoing there is a need to improve the method of forming the cylindrical lower electrode of a capacitor.